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SN74LS373, SN74LS374 Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output
The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all ON Semiconductor TTL families.
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LOW POWER SCHOTTKY
MARKING DIAGRAMS
SN74LS37xN AWLYYWW
20 1 1
* * * * * * *
Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Hysteresis on Latch Enable Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Hysteresis on Clock Input to Improve Noise Margin Input Clamp Diodes Limit High Speed Termination Effects
PDIP-20 N SUFFIX CASE 738
20
LS37x AWLYYWW
1
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current - High Output Current - Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 -2.6 24 Unit V C mA mA
20
1
SOIC-20 DW SUFFIX CASE 751D
74LS37x AWLYWW
1
SOEIAJ-20 M SUFFIX CASE 967 x A WL YY WW
1
= 3 or 4 = Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2001
1
October, 2001 - Rev. 8
Publication Order Number: SN74LS373/D
SN74LS373, SN74LS374
CONNECTION DIAGRAM DIP (TOP VIEW)
SN74LS373
VCC O7 20 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 LE 11 VCC O7 20 19 D7 18
SN74LS374
D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 CP 11
1 OE
2 O0
3 D0
4 D1
5 O1
6 O2
7 D2
8 D3
9 O3
10 GND
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In Line Package.
1 OE
2 O0
3 D0
4 D1
5 O1
6 O2
7 D2
8 D3
9 O3
10 GND
LOADING (Note a) PIN NAMES D0 - D7 LE CP OE O0 - O7 Data Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH Going Edge) Input Output Enable (Active LOW) Input Outputs HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 U.L.
NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
TRUTH TABLE LS373
Dn H L X X LE H H L X OE L L L H On H L Q0 Z* Dn H L X X
LS374
LE OE L L H On H L Z*
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance * Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
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2
SN74LS373, SN74LS374
LOGIC DIAGRAMS SN74LS373
3 4 7 8 13 14 17 18
VCC = PIN 20 GND = PIN 10
D0 D
LATCH ENABLE
D1 Q G D Q G
D2 D Q G
D3 D Q G
D4 D Q G
D5 D Q G
D6 D Q G
D7 D Q G
= PIN NUMBERS
11
LE OE O0
2 5
1
O1
6
O2
9
O3
12
O4
15
O5
16
O6
19
O7
SN74LS374
3 11 4 7 8 13 14 17 18
D0 CP D QQ CP D QQ
D1 CP D QQ
D2 CP D QQ
D3 CP D QQ
D4 CP D QQ
D5 CP D QQ
D6 CP D QQ
D7
CP
OE
1 2
O0
5
O1
6
O2
9
O3
12
O4
15
O5
16
O6
19
O7
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.4 -0.65 3.1 0.25 VOL IOZH IOZL IIH IIL IOS Output LOW Voltage 0.35 Output Off Current HIGH Output Off Current LOW Input HIGH Current Input LOW Current Short Circuit Current (Note 1) -30 0.5 20 -20 20 0.1 -0.4 -130 V A A A mA mA mA 0.4 Min 2.0 0.8 -1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = -18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table
VCC = MAX, VOUT = 2.7 V VCC = MAX, VOUT = 0.4 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX
ICC Power Supply Current 40 mA 1. Not more than one output should be shorted at a time, nor for more than 1 second.
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SN74LS373, SN74LS374
AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)
Limits LS373 Symbol fMAX tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay, Data to Output Clock or Enable to Output Output Enable Time Output Disable Time 12 12 20 18 15 25 12 15 18 18 30 30 28 36 20 25 15 19 20 21 12 15 28 28 28 28 20 25 Min Typ Max Min 35 LS374 Typ 50 Max Unit MHz ns ns ns ns CL = 5.0 pF CL = 45 pF pF, RL = 667 Test Conditions
AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)
Limits LS373 Symbol tW ts th Clock Pulse Width Setup Time Hold Time Parameter Min 15 5.0 20 Max Min 15 20 0 LS374 Max Unit ns ns ns
DEFINITION OF TERMS
SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to LE transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.
HOLD TIME (th) -- is defined as the minimum time following the LE transition from HIGH-to-LOW that the logic level must be maintained at the input in order to ensure continued recognition.
SN74LS373 AC WAVEFORMS
tW LE 1.3 V ts Dn tPLH OUTPUT tPHL th tW
Figure 1.
OE tPZL VOUT 1.3 V 0.5 V 1.3 V 1.3 V tPLZ 1.3 V VOL OE tPZH VOUT 1.3 V 1.3 V tPHZ 1.3 V VOH 1.3 V 0.5 V
Figure 2.
Figure 3.
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4
SN74LS373, SN74LS374
SN74LS373 AC LOAD CIRCUIT
VCC RL SW1 TO OUTPUT UNDER TEST
SWITCH POSITIONS
SYMBOL tPZH tPZL tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed
5.0 k CL* SW2
* Includes Jig and Probe Capacitance.
Figure 4.
SN74LS374 AC WAVEFORMS
tWH CP 1.3 V ts Dn tPLH OUTPUT 1.3 V 1.3 V tPHL 1.3 V tWL 1.3 V OE tPZL VOUT 1.3 V 0.5 V
1.3 V th
1.3 V
1.3 V tPLZ 1.3 V VOL
Figure 6.
Figure 5.
OE tPZH VOUT
1.3 V tPHZ 1.3 V
1.3 V VOH 1.3 V 0.5 V
Figure 7.
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5
SN74LS373, SN74LS374
SN74LS374 AC LOAD CIRCUIT
VCC RL SW1 TO OUTPUT UNDER TEST
SWITCH POSITIONS
SYMBOL tPZH tPZL tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed
5.0 k CL* SW2
* Includes Jig and Probe Capacitance.
Figure 8.
DEVICE ORDERING INFORMATION
Device Order Number SN74LS373N SN74LS373DW SN74LS373DWR2 SN74LS373M SN74LS373MEL SN74LS374N SN74LS374DW SN74LS374DWR2 SN74LS374M SN74LS374MEL Package Type PDIP-20 SOIC-WIDE SOIC-WIDE SOEIAJ-20 SOEIAJ-20 PDIP-20 SOIC-WIDE SOIC-WIDE SOEIAJ-20 SOEIAJ-20 Tape and Reel Size 1440 Units/Box 38 Units/Rail 2500/Tape and Reel See Note 2 See Note 2 1440 Units/Box 38 Units/Rail 2500/Tape and Reel See Note 2 See Note 2
2. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative.
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SN74LS373, SN74LS374
PACKAGE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E
-A-
20 1 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
B
10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
D SUFFIX PLASTIC SOIC PACKAGE CASE 751D-05 ISSUE F
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
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L
SN74LS373, SN74LS374
PACKAGE DIMENSIONS
M SUFFIX SOEIAJ PACKAGE CASE 967-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.81 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.032
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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SN74LS373/D

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